FPGA devices have grown to ASIC size and complexity, but traditional EDA tools and methodologies have failed to keep pace. Engineers designing high-end FPGAs are beginning to face the types of ...

San Francisco, CA – July 27, 2009 — ATopTech, Inc., the primary technology leader in integrated circuit (IC) physical design solutions addressing the challenges of designing ICs at 65 nanometers and ...

Hierarchical design methodologies that introduce concurrency into the design flow are the answer to burgeoning circuit complexity. Synopsys's Steve Kister discusses various challenges to design ...